What is the distinction between computer organization and computer architecture?

What, in general terms, is the distinction between computer organization and computer
architecture?

1)
    Computer architecture refers to those attributes of a system visible to a programmer or, put another way, those attributes that have a direct impact on the logical execution of a program.

    Computer organization refers to the operational units and their interconnections that realize the architectural specifications.

2)
     Examples of architectural attributes include the instruction set, the number of bits used to represent various data types (e.g., numbers, characters), I/O mechanisms, and techniques for addressing memory.

    Organizational attributes include those hardware details transparent to the programmer, such as control signals; interfaces between the computer and peripherals; and the memory technology used.

3)
For example,
    it is an architectural design issue whether a computer will have a multiply instruction.
    It is an organizational issue whether that instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.The organizational decision may be based on the anticipated frequency of use of the multiply instruction, the relative speed of the two approaches, and the cost and physical size of a special multiply unit.

4)
Many computer manufacturers offer a family of computer models, all with the same architecture but with differences in organization.

5)
a particular architecture may span many years and encompass a number of different computer models, its organization changing with changing technology

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The hypothetical machine has two I/O instructions: 0011= Load AC fro I/O 0111= Store AC to I/O Solutions

Problem Set :

The hypothetical machine of figure 3.4 also has two I/O instructions:
0011= Load AC fro I/O
0111= Store AC to I/O
In these cases the 12-bit address identifies a particular I/O device. Show the program execution (using format of figure 3.5) for the following program:
1. Load AC from device 5.
2. Add contents of memory location 940.
3. Store AC to device 6.
Assume that the next value received from device 5 is 3 and that location 940 contains value of 2.

Solution:

Figure (Say)

We will assume that the memory (contents in hex) as the previous table:
300: 3005; 301: 5940; 302: 7006
Therefore, the steps will be as the following:
Step 1: 3005 → IR
Step 2: 3 → AC
Step 3: 5940 → IR
Step 4: 3 + 2 = 5 → AC
Step 5: 7006 → IR
Step 6: AC → Device 6

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Consider a hypothetical 32-bit microprocessor having 32-bit instructions: Solutions

Consider a hypothetical 32-bit microprocessor having 32-bit instructions: Solutions
Problem Set:

Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: the first byte contains the opcode and the remainder the immediate operand or an operand address.
a. What is the maximum directly addressable memory capacity (in bytes)?
b. Discuss the impact on the system speed if the microprocessor bus has
   1. a 32-bit local address bus and a 16-bit local data bus, or
   2. a 16-bit local address bus and a 16-bit local data bus.
   c. How many bits are needed for the program counter and the instruction register?

Solution:

a. 2^(32-8) = 2^24 = 16,777,216 bytes = 16 MB ,(8 bits = 1 byte for he opcode).

b.1. a 32-bit local address bus and a 16-bit local data bus. Instruction and data transfers would take three bus cycles each, one for the address and two for the data. Since If the address bus is 32 bits, the whole address can be transferred to memory at once and decoded there; however, since the data bus is only 16 bits, it will require 2 bus cycles (accesses to memory) to fetch the 32-bit instruction or operand.

b.2. a 16-bit local address bus and a 16-bit local data bus. Instruction and data transfers would take four bus cycles each, two for the address and two for the data. Therefore, that will have the processor perform two transmissions in order to send to memory the whole 32-bit address; this will require more complex memory interface control to latch the two halves of the address before it performs an access to it. In addition to this two-step address issue, since the data bus is also 16 bits, the microprocessor will need 2 bus cycles to fetch the 32-bit instruction or operand.

c. For the PC needs 24 bits (24-bit addresses), and for the IR needs 32 bits (32-bit addresses).

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List and briefly define two approaches to dealing with multiple interrupts

List and briefly define two approaches to dealing with multiple interrupts

Two approaches can be taken to dealing with multiple interrupts. 

First Approach to dealing with multiple interrupts:

The first is to disable interrupts while an interrupt is being processed. A disabled interrupt simply means that the processor can and will ignore that interrupt request signal. If an interrupt occurs during this time, it generally remains pending and will be checked by the processor after the processor has enabled interrupts.Thus, when a user program is executing and an interrupt occurs, interrupts are disabled immediately. After the interrupt handler routine completes, interrupts are enabled before resuming the user program, and the processor checks to see if additional interrupts have occurred.This approach is nice and simple, as interrupts are handled in strict sequential order.

List and briefly define two approaches to dealing with multiple interrupts

Second Approach to dealing with multiple interrupts:

A second approach is to define priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be itself interrupted . As an example of this second approach, consider a system with three I/O devices: a printer, a disk, and a communications line, with increasing priorities of 2, 4, and 5, respectively. Based on an example in [TANE97], illustrates a possible sequence. A user program begins at t 0. At t 10, a printer interrupt occurs; user information is placed on the system stack and execution continues at the printer interrupt service routine (ISR).While this routine is still executing, at t 15, a communications interrupt occurs. Because the communications line has higher priority than the printer, the interrupt is honored. The printer ISR is interrupted, its state is pushed onto the stack, and execution continues at the communications ISR. While this routine is executing, a disk interrupt occurs (t 20). Because this interrupt is of lower priority, it is simply held, and the communications ISR runs to completion.

List and briefly define two approaches to dealing with multiple interrupts

When the communications ISR is complete (t 25), the previous processor state is restored, which is the execution of the printer ISR. However, before even a single instruction in that routine can be executed, the processor honors the higherpriority disk interrupt and control transfers to the disk ISR. Only when that routine is complete (t 35) is the printer ISR resumed.When that routine completes (t 40), control finally returns to the user program.


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List and briefly define two approaches to dealing with multiple interrupts

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List and briefly define the possible states that define an instruction execution

Solution of List and briefly define the possible states that define an instruction execution :

1) Instruction address calculation (iac): 

Determine the address of the next instruction to be executed. Usually, this involves adding a fixed number to the address of the previous instruction. For example, if each instruction is 16 bits long and memory is organized into 16-bit words, then add 1 to the previous address. If, instead, memory is organized as individually addressable 8-bit bytes, then add 2 to the previous address.

2) Instruction fetch (if): 

Read instruction from its memory location into the processor.

3) Instruction operation decoding (iod): 

Analyze instruction to determine type of operation to be performed and operand(s) to be used.

List and briefly define the possible states that define an instruction execution

4) Operand address calculation (oac): 

If the operation involves reference to an operand in memory or available via I/O, then determine the address of the operand.

5) Operand fetch (of): 

Fetch the operand from memory or read it in from I/O.

6) Data operation (do):

 Perform the operation indicated in the instruction.

7) Operand store (os):

 Write the result into memory or out to I/O.

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